mcp4eda

mcp4eda - MCP Servers for Electronic Design Automation

A comprehensive collection of Model Context Protocol (MCP) servers designed to enhance EDA workflows in Claude Desktop and other MCP-compatible clients.

Purpose:Synthesis and design optimization for digital circuits
Location:yosys-mcp/

- Synthesize Verilog/SystemVerilog to gate-level netlists
- Support for multiple FPGA targets (Xilinx, Intel/Altera, Lattice)
- Design analysis (hierarchy, resources, statistics)
- Circuit visualization generation
- Intelligent caching for performance

- yosys_synth- Synthesis with multiple output formats
- yosys_analyze- Design analysis and statistics
- yosys_show- Generate visual circuit diagrams

Purpose:High-performance RTL simulation and verification
Location:verilator-mcp/

- Fast Verilog/SystemVerilog simulation
- Automatic testbench generation
- Natural language debugging interface
- Coverage collection and analysis
- Waveform generation support

- verilator_compile- Compile designs to C++
- verilator_simulate- Run simulations with auto-testbench
- verilator_testbenchgenerator- Intelligent testbench creation
- verilator_naturallanguage- Natural language queries

Purpose:SystemVerilog/Verilog linting, formatting, and analysis
Location:verible-mcp/

- Comprehensive style linting with auto-fix
- Code formatting with customizable rules
- Syntax tree analysis and visualization
- Register and module analysis
- Project-level dependency analysis
- Natural language interface

- verible_lint- Style checking and fixes
- verible_format- Code formatting
- verible_syntax- AST analysis
- verible_analyze- Design analysis
- verible_natural_language- Natural language queries

Purpose:Waveform viewing and analysis automation
Location:gtkwave-mcp/

- Programmatic waveform viewing
- Format conversion (VCD, FST, LXT2)
- Signal hierarchy extraction
- Timing analysis and measurements
- Screenshot generation
- TCL script generation

- gtkwave_open- Open waveforms with configurations
- gtkwave_convert- Convert between formats
- gtkwave_extract_signals- Extract signal hierarchies
- gtkwave_analyze_timing- Timing measurements
- gtkwave_capture_screenshot- Generate waveform images

Purpose:IC layout viewing, editing, and analysis
Location:klayout-mcp/

- Multi-format support (GDS, OASIS, DXF, CIF, MAG, DEF/LEF)
- Design Rule Checking (DRC) with powerful engine
- Layer extraction and manipulation
- Format conversion with scaling
- Custom Python/Ruby scripting
- Natural language interface
- Rich resource library

- klayout_layout_info- Analyze layout files
- klayout_convert_layout- Format conversion
- klayout_run_drc- Design rule checking
- klayout_extract_layers- Layer extraction
- klayout_execute_script- Custom scripting
- klayout_natural_language- Natural language queries

Purpose:Semiconductor manufacturing calculations
Location:anysilicon/

- Die per wafer calculations
- Support for multiple wafer sizes (150mm-450mm)
- Edge exclusion and scribe lane parameters
- Integration with AnySilicon's web calculator
- Yield estimation support

- calculate_die_per_wafer- Calculate die yield
- validate_parameters- Validate input parameters
- get_standard_wafer_sizes- Get wafer standards

Purpose:IP core and ASIC service procurement intelligence
Location:semiconductor-supply-chain-mcp/

- Find IP vendors by category and technology
- Locate ASIC design and manufacturing services
- Price estimation for semiconductor services
- Multi-vendor comparison
- Natural language queries for complex searches

- find_ip_vendors- Search IP core vendors
- find_asic_services- Find ASIC services
- get_price_estimation- Estimate costs
- compare_vendors- Compare multiple vendors
- natural_language_query- Natural language interface

Purpose:Complete RTL to GDSII flow automation
Location:openlane-mcp/

- Complete RTL to GDSII flow using OpenLane
- Container-based execution (Docker/Podman)
- Individual stage control (synthesis, placement, routing)
- PDK management and configuration
- Natural language interface for complex flows

- openlane_run_flow- Complete RTL to GDSII flow
- openlane_run_synthesis- Logic synthesis
- openlane_run_floorplan- Floorplanning and I/O placement
- openlane_run_placement- Standard cell placement
- openlane_run_cts- Clock tree synthesis
- openlane_run_routing- Global and detailed routing
- openlane_natural_language- Natural language interface

All 8 MCP servers now include comprehensivenatural language interfaces, allowing you to interact with EDA tools using plain English commands:

"Synthesize my design for Xilinx FPGA" "Run simulation for 1 microsecond" "Check my Verilog for errors" "Generate testbench for my CPU module" "Show waveform of clock signals" "Convert layout to OASIS format" "Calculate dies per wafer for 10x10mm chip" "Find DDR5 IP vendors" "Run complete RTL to GDSII flow"

SeeNatural Language Support Guidefor comprehensive examples and patterns.

git clone https://github.com/ssql2014/mcp4eda.git cd mcp4eda

# Install script for all servers for dir in yosys-mcp verilator-mcp verible-mcp gtkwave-mcp klayout-mcp anysilicon semiconductor-supply-chain-mcp openlane-mcp; do echo "Installing $dir..." cd $dir && npm install && npm run build && cd .. done

{ "mcpServers": { "yosys": { "command": "node", "args": ["/path/to/mcp4eda/yosys-mcp/dist/index.js"], "env": { "YOSYS_PATH": "/opt/homebrew/bin/yosys", "LOG_LEVEL": "info" } }, "verilator": { "command": "node", "args": ["/path/to/mcp4eda/verilator-mcp/dist/index.js"], "env": { "VERILATOR_PATH": "/opt/homebrew/bin/verilator", "LOG_LEVEL": "info" } }, "verible": { "command": "node", "args": ["/path/to/mcp4eda/verible-mcp/dist/index.js"], "env": { "LOG_LEVEL": "info" } }, "gtkwave": { "command": "node", "args": ["/path/to/mcp4eda/gtkwave-mcp/dist/index.js"], "env": { "GTKWAVE_PATH": "/opt/homebrew/bin/gtkwave", "LOG_LEVEL": "info" } }, "klayout": { "command": "node", "args": ["/path/to/mcp4eda/klayout-mcp/dist/index.js"], "env": { "KLAYOUT_PATH": "/opt/homebrew/bin/klayout", "LOG_LEVEL": "info" } }, "anysilicon": { "command": "node", "args": ["/path/to/mcp4eda/anysilicon/dist/index.js"] }, "semiconductor-supply-chain": { "command": "node", "args": ["/path/to/mcp4eda/semiconductor-supply-chain-mcp/dist/index.js"] }, "openlane": { "command": "node", "args": ["/path/to/mcp4eda/openlane-mcp/dist/index.js"], "env": { "CONTAINER_EXECUTABLE": "docker", "OPENLANE_IMAGE": "efabless/openlane:latest", "WORK_DIR": "/path/to/openlane-workspace", "LOG_LEVEL": "info" } } } }

User: "Check DRC on my layout.gds" Claude: [Uses KLayout to run design rules] User: "Calculate die yield for 10x10mm chip on 300mm wafer" Claude: [Uses AnySilicon for yield calculation] User: "Find DDR5 PHY IP vendors" Claude: [Uses Supply Chain MCP to search vendors]

tail -f ~/Library/Logs/Claude/mcp-server-.log

# Check all tools which yosys verilator verible gtkwave klayout # Test MCP servers for server in /dist/index.js; do echo "Testing $server" timeout 2 node "$server" 2>&1 | head -n 5 done

- Magic MCP: Layout editor integration
- OpenROAD MCP: Complete RTL-to-GDS flow
- ngspice MCP: Circuit simulation
- Icarus MCP: Alternative Verilog simulator

- Cross-tool workflow automation
- Cloud synthesis and simulation
- Project templates and wizards
- CI/CD integration for hardware
- Fork the repository
- Create a feature branch (git checkout -b feature/NewMCP)
- Implement your MCP server following the existing patterns
- Add comprehensive documentation
- Submit a pull request

SeeCONTRIBUTING.mdfor detailed guidelines.

- MCP4EDA Website
- Model Context Protocol Docs
- Claude Desktop
- GitHub Repository

MCP server that gives AI assistants on-demand access to 1,500+ amCharts docs, ~300 code examples, and 1000+ class API references.